1. Field of the Invention
The invention relates to a delay lock loop (DLL) circuit and related method, and more particularly, to a jitter-resistive digital DLL circuit and related method for delaying a reference clock to lock a delayed clock through detecting one phase change.
2. Description of the Prior Art
Delay lock loop (DLL) circuitry is commonly utilized in computer processing environments for generating a required clock. While the clock rate of computers continually is increasing, low-skew clock distributions are becoming more important to achieve design speed objectives. Related art computer systems include processors that exchange data with a variety of memory devices and input/output peripheral devices. An exemplary memory device is a synchronous dynamic random access memory (SDRAM) employing a pipelined data to be transferred to the processor at a data transfer rate which is comparable to the processor's operating frequency. In a DDR memory application, data are outputted from a DDR SDRAM to a memory controller at both rising and falling edges of a clock cycle. However, the DLL implemented in the memory controller is designed to generate a delayed clock according to a memory clock for delaying the timing of latching the data which is inputted to the memory controller. That is, the DLL provides an amount of delay that appropriately shifts the original rising and falling edges of the memory clock. As a result, the memory controller is capable of storing correct data into the latched device.
FIG. 1 is a block diagram of a digital DLL 10 according to the related art. The DLL 10 includes a delay line 12 having a plurality of serially connected delay cells 13, a 360° phase detector 14, and a DLL controller 16. Each of the delay cell 13 is used to provide an amount of delay dt. Therefore, if the number of delay cells 13 in the delay line 12 is K, the total amount of the delay time on the input clock CLKi is equal to K*dt. A delayed clock CLKd and the input clock CLKi are delivered to the 360° phase detector 14. The related art 360° phase detector 14 outputs a notification signal Sc to the DLL controller 16 when detecting a 180° phase difference (i.e. the phase change) between the delayed clock CLKd and the input clock CLKi twice. That is, the notification signal Sc informs the DLL controller 16 of the situation that the delayed clock CLKd is 360° lagging behind the input clock CLKi. Therefore the DLL controller 16 continuously programs the amount of delay dt of each delay cell 13 to increase the total amount of delay on the input clock CLKi until the notification signal Sc is generated from the 360° phase detector 14. The operation of the DLL 10 is further detailed as follows.
FIG. 2 is a simplified timing diagram illustrating the operation of the DLL 10 shown in FIG. 1. As mentioned above, the delay line 12 provides the input clock CLKi with a programmable amount of delay, and then outputs the delayed clock CLKd. At t1, the rising edge of the input clock CLKi is inputted into the delay line 12. With a proper control commanded by the DLL controller 16, the delay line 12 provides an amount of delay dT1 to the input clock CLKi. Therefore, the rising edge of the delayed clock CLKd is outputted from the delay line 12 at t2. Because the notification signal Sc is not generated from the 360° phase detector 14 yet, the DLL controller 16 controls the delay line 12 to gradually increase the amount of delay imposed upon the input clock CLKi. As shown in FIG. 2, an amount of delay dT2 (dT2>dT1) between t3 and t4, an amount of delay dT3 (dT3>dT2) between t5 and t6, and an amount of delay dT4 (dT4>dT3) between t7 and t8 are generated, respectively. Please note that if the 360° phase detector 14 is triggered by rising edges of the input clock CLKi, the logic values detected by the 360° phase detector 14 at t1, t3, t5, t7, and t9 are “0”, “0”, “0”, “0”, and “1”. Therefore the 360° phase detector 14 judges that one 180° phase difference between the delayed clock CLKd and the input clock CLKi occurs at t9.
Because the notification signal Sc is not generated from the 360° phase detector 14 yet, the DLL controller 16, as mentioned above, keeps commanding the delay line 12 to gradually increase the amount of delay imposed upon the input clock CLKi. As shown in FIG. 2, an amount of delay dT5 (dT5>dT4) between t9 and t10, an amount of delay dT6 (dT6>dT5) between t11 and t12, an amount of delay dT7 (dT7>dT6) between t13 and t14 are generated, and an amount of delay dT9 (dT6>dT7) between t15 and t16 are generated, respectively. As one can see, the logic values detected by the 360° phase detector 14 at t11, t13, t15, and t16 are “1”, “1”, “1”, and “0”. Therefore the 360° phase detector 14 judges that another 180° phase difference between the delayed clock CLKd and the input clock CLKi occurs at t16. Because detecting the 180° phase difference between the delayed clock CLKd and the input clock CLKi twice, the 360° phase detector 14 triggers the notification signal Sc to inform the DLL controller 16. Assume that the number of delay cells 13 in the delay line 12 is K, and one period of the input clock CLKi is T. Therefore, the setting for the delay line 12 delaying the input clock CLKi by the amount of delay dT8, which is equal to T, is capable of forcing each delay cell 13 to has an amount of delay equaling
      T    K    .In other words, after the DLL 10 has successfully lock the delayed clock CLKd 360° lagging behind the input clock CLKi, an output of an Nth delay cell within the delay line 12 corresponds to an amount of delay equal to
  N  *            T      K        .  
However, the DLL 10 shown in FIG. 1 does little to resist the effects of jitter. Jitter, a term familiar to those skilled in the art, refers to any deviation of amplitude, phase timing, or the width of signal pulse. Alternatively, jitter is defined as “the period frequency displacement of the signal from its ideal location”. Jitter is typically caused by electromagnetic interference and cross talk with other signals. The effect of jitter on the DLL 10 results in erroneous delayed clocks, thereby making the DLL 10 malfunction to lock a wrong phase difference. Referring to FIG. 2, the effects of jitter on the DLL 10 advance the timing of a falling edge ideally occurring at t11. Therefore, jitter causes the 360° phase detector 14 to detect a 180° phase difference at t′ and erroneously triggers the notification signal Sc. As a result, each delay cell 13 does not provide a wanted amount of delay equaling
      T    K    .Therefore, an application device is unable to function normally due to an improper delayed clock generated from the delay line 12 of the related art DLL 10.